The present application relates to semiconductor device fabrication, and more particularly to the formation of trench gate structures for field effect transistors (FETs) using a gate first process.
Transistors, such as field effect transistors (FETs), are the basic elements of microelectronics and integrated circuits. A FET typically includes a gate structure overlying a channel region of a semiconductor substrate and a source region and a drain region located in the semiconductor substrate and spaced apart by the channel region. The gate structure includes a gate electrode over a gate dielectric. By applying an appropriate voltage to the gate electrode, the channel region becomes conductive and current is allowed to flow from the source region to the drain region. The gate structure can be formed using a “gate first” process, or a “gate last” process. Gate first refers to a fabrication process in which line-type gate structures are formed by lithographically patterning a gate material stack of a gate dielectric layer and a gate electrode before device activation. Gate last refers to a fabrication process in which line-type sacrificial gate structures are first fabricated by lithography and etching, and then replaced with metal gate structures after device activation.
To reduce power consumption and increase switching speed, integrated circuits are continuously being scaled down. FETs thus tend to get smaller and more densely packed, raising a variety of problems for integration. For example, as the gate pitch continues to shrink, the aspect ratios of the line-type gate or sacrificial gate structures are increased. These free-standing line-type gate or sacrificial gate structures are therefore vulnerable to tilting or collapsing, causing device shorting and reducing device yield. Therefore, a method remains needed to fabricate more robust gate structures, reducing the risk of tilting or collapsing of the gate structures.